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1 ? ISL6224 single output mobi le-friendly pwm controller the ISL6224 provides power contro l and protection for a single, adjustable output voltage required to power chip-sets and memory banks in high-performance notebooks and pdas. this output voltage is adjustable in the range from 0.9-5.5v. the hysteretic or pwm controller regulates the output voltage from battery voltages ranging from 4v to 24v. synchronous rectification and hy steretic operation at light loads contribute to a high efficiency over a wide range of input voltages and loads. efficiency is even further enhanced by using mosfet?s r ds(on ) as a current sense component. feed-forward ramp modulation, average current mode control and internal feed-ba ck compensation provide fast and firm handling of transients when powering advanced chip sets. two-stage conversion using syst em 5v voltage is possible at a higher frequency (600khz) to minimize the output filter size. the ISL6224 monitors the outpu t voltage. a pgood (power good) signal is issued when soft-start is completed and the output is within 10% of the set point. a built-in overvoltage protecti on prevents output voltage from going above 120% of the set point. undervoltage protection latches the chip off when the output drops below 70% of its setting value after soft-start sequence is completed. the pwm controlle r?s overcurrent circuitry monitors the output current by sensing the voltage drop across the lower mosfet. if higher precision sense technique is required, an opt ional external current-sense resistor may be used. features ? adjustable output voltgage: 0.9-5.5v ? high efficiency over wide load range - higher efficiency in hysteretic mode at light load ? lossless current sense scheme - uses mosfet?s r ds(on) - optional current sense method higher precision ? supply operation mode - wide v in range: 4v-24v - single 5v system rail ? input undervoltage lock-out on vcc pin(uvlo) ? excellent dynamic response - combined voltage feed-forward and current mode control ? power-good indicator ? 300/600khz switching frequency ? thermal shut-down ? pb-free available applications ? mobile pcs ? graphic cards ? hand-held portable instruments related literature ? application note an9983 pinout ISL6224 (ssop) top view ordering information part number temp. (c) package pkg. dwg. # ISL6224ca -10 to 85 16 ld ssop m16.15a ISL6224caz (note 1) -10 to 85 16 ld ssop (pb-free) m16.15a note: 1. intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. 2. add ?-t? for tape and reel. en gnd isen vcc vsen lgate pgnd vin boot ugate phase pgood 14 13 12 11 10 9 1 2 3 4 5 6 7 8 soft ocset 15 16 vout fccm fn9042.6 data sheet april 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 absolute maximum rati ngs thermal information bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v input voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0v phase and isen pins . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to +29.0v boot and ugate pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 32.0v boot with respect to phase . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to 15v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 recommended operating conditions bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0v 5% input voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0v to +24.0v ambient temperature range . . . . . . . . . . . . . . . . . . . .-10c to 85c junction temperature range. . . . . . . . . . . . . . . . . . .-10c to 125c thermal resistance (typical, note 1) ja (c/w) ssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (ssop - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications operating conditions: v cc = 5v, t a = 10c to 85c, unless otherwise noted. parameter symbol test conditions min typ max units vcc supply bias current i cc lgate, ugate open, vsen forced above regulation point - 850 1300 a shutdown current i ccsn -515 a vcc uvlo rising vcc threshold 4.3 - 4.75 v falling vcc threshold 4.1 - 4.5 v vcc uvlo hysteris 0.1 - 0.5 v vin input voltage pin current (sink) i vin vin pin connected to the input voltage source 10 20 30 a input voltage pin current (source) i vin vin pin connected to ground -7 -15 -20 a shutdown current i vin --1 a oscillator pwm oscillator frequency f c1 v in = 3.5v - 24v 255 300 345 khz pwm oscillator frequency f c2 v in 0.5v 510 600 690 khz ramp amplitude, pk-pk v r1 v in = 16v, by design - 2 - v ramp amplitude, pk-pk v r2 v in 5v, by design - 1.25 - v ramp offset v roff -0.5- v reference and soft-start internal reference voltage v ref -0.9- v reference voltage accuracy -1.0 - +1.0 % soft-start current during start-up i soft -5- a soft-start threshold v soft -1.5- v pwm converter load regulation 0.0ma < i vout1 < 3.0a; 5.0v < v in < 24.0v -1.0 - +1.0 % vsen pin bias current i vsen -80- na ISL6224
3 vout pin input impedance i vout 40 55 65 k ? undervoltage shutdown level v uv1 fraction of the set point; ~3 s noise filter 70 - 80 % overvoltage protection v ovp1 fraction of the set point; ~1 s noise filter 113 - 120 % pwm controller gate drivers upper drive pull-up resistance r 2ugpup -815 ? upper drive pull-down resistance r 2ugpdn -3.25 ? lower drive pull-up resistance r 2lgpup -815 ? lower drive pull-down resistance r 2lgpdn -1.52.4 ? power good and control functions power-good lower threshold v pg- fraction of the set point; ~3 s noise filter -14 - -8 % power-good higher threshold v pg+ fraction of the set point; ~3 s noise filter 10 - 15 % pgood leakage current i pglkg v pullup = 5.5v - - 1 a pgood voltage low i pgood = -4ma - - 0.5 v en - low (off) --0.8v en - high (on) 2.0 - - v fccm -hysteretic operation enabled - vcc/2 - v electrical specifications operating conditions: v cc = 5v, t a = 10c to 85c, unless otherwise noted. (continued) parameter symbol test conditions min typ max units ISL6224
4 functional block diagram power-on reset (por) ramp clk clk + - ea1 + - ref lgate1 + volt- clamp oc logic1 + - d < q q r vcc boot ugate phase lgate pgnd vcc lgdr hgdr1 gate control hi lo gate logic pwm on pwm/hyst deadt shutoff + - lgate r1=20k vsen isen - pwm latch 1 oc comp1 hyst on + - hyst comp1 clk1 + - ffbk second gnd por output voltage monitor ovp mode change comp reference and soft-start ref por sdwn en vcc fset fccm ocset fccm pgood vin soft pwm/hys logic v out ISL6224
5 functional pin description vin (pin 1) provides battery voltage to the oscillator for feed-forward rejection of the input voltage variation. also, this pin programs frequency of the internal clock and gain of the ramp generator. when connecte d to the battery, which voltage varies from 4v to 24v, the clock frequency is set to 300khz and the ramp gain is set accordingly to accommodate the wide input voltage range. for two step conversion from the system 5v power rail, the vin pin is connected to ground via a 150k ? resistor. this arrangement changes the gain of the ramp generator to accommodate the lower input voltage but does not change the clock frequency. when the vin pin is connected to ground, the clock frequency is set to 600khz. the ramp generator gain is also changed accordingly. this circuit arrangement enables the designer to choose smaller output filter components. pgood (pin 2) pgood is an open collector output used to indicate the status of the output voltage. this pin is pulled high when the system output is within 10% of its respective nominal voltage. en (pin 3) this pin provides the enable/disable function for the chip. the ic is enabled when this pin is pulled over 2v or left open. note: a pulldown resistance of 100k ? or less is required to disable the controller. ocset (pin 4) a resistor from this pin to gnd sets the overcurrent protection threshold. vout (pin 5) this pin is used for feedback of the output voltage to properly position output voltage during operational mode change. vsen (pin 6) this pin is connected to the out put via a resistive divider and provides the voltage feedback signal for the pwm controller. the pgood, uvp, and ovp circuits use this signal to report output voltage status. soft (pin 7) this pin provides soft-start of the pwm controller. when the en pin is pulled high, the voltage on the capacitor connected to the soft-start pin is rising linearly due to the 5 a pull-up current. the output voltage follows the voltage on the capacitor until it reaches the value of 0.9v. the further rise of the voltage on the soft-start capacitor does not affect the output voltage. gnd (pin 8) signal ground for the ic. pgnd (pin 9) this is the power ground connection for pwm converter. this pin is connected to the lower mosfet?s source terminal. lgate (pin 10) this pin provides the gate drive for the lower mosfet. vcc (pin 11) this pin provides power to the chip. isen (pin 12) this pin is used to monitor the voltage drop across the lower mosfet for current feedback and overcurrent protection. for precise current detection this input can be connected to an optional current sense resistor placed in series with the source of the lower mosfet. phase (pin 13) connect this pin to the phase node of the converter. the phase node is the junction point of the upper mosfet source, output filter inductor, and lower mosfet drain. ugate (pin 14) this pin provides the gate drive for the upper mosfet. boot (pin 15) this pin powers the upper mosfet drivers of the pwm converter. connect this pin to the junction of bootstrap capacitor with the cathode of the bootstrap diode. anode of the bootstrap diode is connected to the vcc pin. fccm (pin 16) this pin, when pulled to vcc, restrains hysteretic operation in light loads. general description operational overview the ISL6224 is a single-channel pwm controller intended for chipset, dram, or other low voltage power needs of modern notebook and sub-noteboo k pcs. the ic integrates control circuits and feedback compensation for a single synchronous buck converter. the output voltage is set in the range of 0.9?5.5v by an external resistive divider. the synchronous buck converter can be configured for either 300khz or 600khz switching frequencies. when operated from battery, a swit ching frequency of 300khz is recommended. when operating from 5v, switching frequencies of 300khz or 600k hz are an option. for 300khz operation, pin 1 should be connected through a resistor (150k) to gnd. for 600khz operat ion, pin 1 should simply be ISL6224
6 grounded. table 1. shows the configuration for different modes of operation. figure 1 bel ow shows plots of the ramp speed compensation. the synchronous converter light-load efficiency is enhanced by a hysteretic mode of operation which is automatically engaged at light loads when the inductor current becomes discontinuous. as the filter inductor resumes continuous current, the pwm mode of ope ration is automatically restored. the ISL6224 control ic employs an average current mode control scheme with input vo ltage feedforward ramp programming for better rejectio n of input voltage variations. current sensing and current limit protection the pwm converter uses the lower mosfet on-state resistance, r ds(on) , as the current-sensing element. this technique eliminates the need for a current sense resistor and the associated power losses. if more accurate current protection is desired, current sense resistors may be used in series with the lower mosfet?s source. a current proportional signal is used to provide average current mode control and overcurrent protection. the gain in the current sense circuit is set by the resistor connected from isen (pin 12) to the phase no de of the buck converter. the value of this resistor can be estimated by the following expression: where iomax is the maximum inductor current. the value of r isen should be specified for the expected maximum operating temperature. an overcurrent protection threshold is set by an external resistor connected from ocset (pin 4) to ground. the value of this resistor can be obtained from the following expression: where ioc is the value of overcurrent. the resulting current out of the isen pin through r isen , is used for current feedback and current limit protection. this is compared with an internal current limit threshold. when a sampled value of the output current is determined to be above the current limit threshold, the pwm drive is terminated and a counter is initiated. this limits the inductor current build-up and essentially switches the converte r into current-limit mode. if an overcurrent is detected between 26ms to 53ms later, an overcurrent shutdown is initiated. if during the 26ms to 53ms period, an overcurrent is not det ected, the counter is reset and sampling continues as normal. this current limit scheme has proven to be very robust in applications like portable co mputers where fast inductor current build-up is common due to a large difference between input and output voltages and a low value of the inductor. light-load (hysteretic) operation in the light-load (hysteretic) mode the output voltage is regulated by the hysteretic co mparator which regulates the output voltage by maintaining the output voltage ripple as shown in figure 2. in hysteret ic mode, the inductor current flows only when the output voltage reaches the lower limit of the hysteretic comp arator and turns off at the upper limit. hysteretic mode saves converte r energy at light loads by supplying energy only at the time when the output voltage requires it. this mode conser ves energy by reducing the power dissipation associated with continuous switching. during the time between inductor current pulses, both the upper and lower mosfets are turned off. this is referred to as ?diode emulation mode? because the lower mosfet performs the function of a diode. this diode emulation mode prevents the output capacitor from discharging through the lower mosfet when the upper mosfet is not conducting. note: the pwm only operation can in tentionally be forced by tying pin 16, fccm, to vcc. table 1. configuration for modes of operation operation pin 1 connection pin 1 potential one-stage 300khz vin v1 > 4v two-stage 300khz 150k-gnd 1v < v1 < 2v two-stage 600khz gnd v1 < 0.5v figure 1. ramp speed compensation vo = 2.5v 300khz clock 600khz clock vo/8 vo/4 vin 8 --------- - t t --- vin 4 --------- - t t --- vin 2 --------- - t t --- risen iomax rdson ? 75 a ------------------------------------------ - 100 ? = rocset 11 risen ? ioc rdson ? --------------------------------- = ISL6224
7 operation-mode control the mode-control circuit chan ges the converter?s mode of operation based on the voltage polarity of the phase node when the lower mosfet is conducting and just before the upper mosfet turns on. for continuous inductor current, the phase node is negative when the lower mosfet is conducting and the converters operate in fixed-frequency pwm mode as shown in figure 3. when the load current decreases to the point where the inductor current flows through the lower mosfet in the ?reverse? direction, the phase node becomes positive, and the mode is changed to hysteretic. a phase comparator handles the timing of the phase node voltage sensing. a low level on the phase comparator output indicates a negative phase voltage during the conduction time of the lower mosfet. a high level on the phase comparator output indicate s a positive phase voltage. when the phase node is positive (phase comparator high), at the end of the lower mosf et conduction time, for eight consecutive clock cycles, the mode is changed to hysteretic as shown in figure 3. the dashed lines indicate when the phase node goes positive and the phase comparator output goes high. the solid vertical lines at 1,2,...8 indicate the sampling time, of the phase comparator, to determine the polarity (sign) of the phase n ode. at the transition between pwm and hysteretic mode both the upper and lower mosfets are turned off. the phase node will ?ring? based on the output inductor and the parasitic capacitance on the phase node and settle out at the value of the output voltage. the mode change from hysteretic to pwm can be caused by one of two events. one event is the same mechanism that causes a pwm to hysteretic tran sition. but instead of looking for eight consecutive positive occurrences on the phase node, it is looking for eight consecutive negative occurrences on the phase node. the operation mode will be changed from hysteretic to pwm when these eight consecutive pulses occur. this transition technique prevents jitter of the operation mode at load levels close to boundary. the other mechanism for changing from hysteretic to pwm is due to a sudden increase in th e output current. this step load causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor esr. if the decrease causes the output voltage to drop below the hysteretic regulation level, the mode is changed to pwm on the next clock cycle. this insures the full power required by the increase in output current. gate control logic the gate control logic transl ates generated pwm control signals into the mosfet gate drive signals providing necessary amplification, level shifting and shoot-through protection. also, it has functions that help optimize the ic performance over a wide range of operational conditions. since mosfet switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to- source voltages of both upper and lower mosfets. the lower mosfet is not turned on until the gate-to-source voltage of the upper mosfet has decreased to less than approximately 1v. similarly, t he upper mosfet is not turned on until the gate-to-source voltage of the lower mosfet has decreased to less than approximately 1v. this allows a wide variety of upper and lower mosfets to be used without a concern for simultaneous conduction, or shoot-through. pwm hysteretic 1 2 3 4 5 6 7 8 vout i l phase comp mode of t t t t figure 2. hysteretic operation mode operation pwm hysteretic 1 2 3 4 5 6 7 8 i l phase comp operation mode of t t t phase node t figure 3. mode control waveforms ISL6224
8 soft-start operation soft-start of the synchronous buck converter is accomplished by means of a capacitor connected from pin 7, soft to ground. the soft-start time can be obtained from the following equation: figure 4 shows the soft-start initiated by the enable pin being pulled high with the vin input at 5.6v and the resulting 3.3v output and pgood signal. while the enable pin is held low, prior to t0, the output is off. when the en pin is pulled high, at t0, the voltage on the capacitor connected to the soft-start pin rises linearly due to the internal 5 a current source starts charging the capacitor. the output voltage follows the voltage on the capacitor till it reaches the value of 0.9v at t1. at this moment, t1, the output voltage started regulation. the soft-start is complete when pgood pin is high at t2 and further rise of the voltage on the soft-start capacitor does not affect the output voltage. power good status the ISL6224 monitors the output voltage. a single power- good signal, pgood, is issued when soft-start is completed and the output is within 10% of it?s set point. after the soft- start sequence is completed, undervoltage protection latches the chip off when any of the monitored outputs drop below 70% of its set point. a ?soft-crowbar? function is implemented for an overvoltage on the output. if the output voltage goes above 120% of its nominal output level, the upper mosfet is turned off and the lower mosfet is turned on. this ?soft-crowbar? condition will be maintained until the output voltage returns to the regulation window and then normal operation will continue. this ?soft-crowbar? and monitoring of the output, prevents the output voltage from ringing negative as the inductor current flows in the ?reverse? direction through the lower mosfet and output capacitors. component selection guidelines output capacitor selection the output capacitors have unique requirements. in general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. selection of the output capacitors is also dependent on the output inductor so some inductor analysis is required to select the outpu t capacitors. one of the parameters limiting the converter?s response to a load transient is the time required for the inductor current to slew to its new level. given a sufficiently fast control loop design, the ISL6224 will provide either 0% or 94% duty cycle in response to a load transient. the response time is the time interval required to slew the inductor current from an initial current value to the load current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). minimizing the response time can minimize the output capacitance required. if the load transient rise time is slower than the inductor response time, as in a hard drive or cd drive, this reduces t he requirement on the output capacitor. the maximum capacitor value required to provide the full, rising step, transient load curre nt during the response time of the inductor is: where: c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input voltage, v out is output voltage, and dv out is the drop in output voltage allowed during the load transient. high frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (equivalent series resistance) and voltage rating requirements as well as actual capacitance requirements. the output voltage ripple is due to the inductor ripple current and the esr of the output capacitors as defined by: where, is calculated in the inductor selection section. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that tss 1.5v css 5.0 a ----------------------------- - = figure 4. mode control waveforms t0 t1 t2 c out l o i tran v in v out ? () 2 --------------------------------------------- - i tran dv out -------------------- = v ripple ? i l esr = ? i l ISL6224
9 could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applicati ons, at 300khz, for the bulk capacitors. in most ca ses, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. the stability requirement on the selection of the output capacitor is that the ?esr zero?, f z , be between 1.2khz and 30khz. this range is set by an internal, single compensation zero at 6khz. the esr zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. therefore: in conclusion, the output capaci tors must meet three criteria: 1. they must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient 2. the esr must be sufficiently low to meet the desired output voltage ripple due to the output inductor current, and 3. the esr zero should be placed, in a rather large range, to provide additional phase margin. output inductor selection the output inductor is selected to meet the output voltage ripple requirements. the inductor value determines the converter?s ripple current and t he ripple voltage is a function of the ripple current and output capacitor(s) esr. the ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by the following equation: where f s is the switching frequency. input capacitor selection the important parameters for the bulk input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maxi mum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. the ac rms input current varies with load. depending on the specifics of the input powe r and it?s impedance, most (or all) of this current is supplied by the input capacitor(s). use a mix of input bypass capaci tors to control the voltage ripple across the mosfets. us e ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capa citors can be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for board designs that allow through-hole components, the sanyo os-con? series offer low esr and good temperature performance. for surface mount designs, solid tantalum capacitors can be used, but caution must be ex ercised with regard to the capacitor surge current rating . these capacitors must be capable of handling the surge-current at power-up. the tps series available from avx is surge current tested. mosfet considerations the logic level mosfets are chosen for optimum efficiency given the potentially wide in put voltage range and output power requirements. one dual n-channel or two n-channel mosfets are used in each of the synchronous rectified buck converters for the outputs. these mosfets should be selected based upon r ds(on) , gate supply requirements, and thermal management considerations. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycle (see the following e quations). the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfet has significant switching losses , since the lower device turns on and off into near-zero voltage. the equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfet?s body diode. the gate-charge losses are dissipated by the ISL6224 and do not heat the mosfets. however, a large gate-charge increases the switching time, t sw which increases the upper mosfet switching losses. ensu re that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. c out 1 2 esr f z ------------------------------------------- = ? i l v in v out ? f s l ------------------------------- - v out v in --------------- - = p upper i o 2 r ds on () v out v in ------------------------------------------------------------ i o v in t sw f s 2 ---------------------------------------------------- + = p lower i o 2 r ds on () v in v out ? () v in -------------------------------------------------------------------------------- - = ISL6224 os-con? is a registered trademark of sanyo electric company, ltd. (japan)
10 layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an example, the turn-off transition of one of the upper pwm mosfets. prior to turn-off, the upper mosfet is carrying the full load current. during the turn-off, current stops flowing in the upp er mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a volt age spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. see the application note an9983 for the evaluation board component placement and the printed circuit board layout details. there are two sets of crit ical components in a dc/dc converter using an ISL6224 controller. the switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of nois e. the critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. power components layout considerations the power components and the controller ic should be placed first. locate the input capacitors, especially the high- frequency ceramic decoupling capacitors, close to the power mosfets. locate the output i nductor and output capacitors between the mosfets and the load. locate the pwm controller close to the mosfets. insure the current paths from the input capacitors to the mosfets, to the output inductor s and output capacitors are as short as possible with maximum allowable trace widths. a multi-layer printed circuit board is recommended. dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes, but do not unnecessarily oversize these particular islands. since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. use the remaining printed circuit layers for small signal wiring. the wiring traces from the control ic to the mosfet gate and source should be sized to carry 2a peak currents. small components signal layout considerations the vin pin 1 input should be bypassed with a 1.0f capacitor. the bypass capacitors for vin and the soft-start capacitor, should be located close to their connecting pins on the control ic. refer to the application note an9983 for a recommended component placement and interconnections. figures 5, 6 and 7 show applicatio n circuits for the three modes of operation. mode 1 is operat ing from battery voltage and operating at 300khz switching frequency. mode 2 is operating off of 5v and operating at 300khz switching frequency. mode 3 is operating off of 5v and operating at 600khz switching frequency. ISL6224
11 ISL6224 dc-dc converter application circuits figure 5 shows an application circuit of a dc/dc converter for a notebook pc. the power supply provides +v2_5s from either +4v?24v dc battery voltage or system +5v bus. for detailed information on the circuit, including a bill of materials and circuit board description, see application note an9983. also see intersil?s web site (h ttp://www.intersil.com) for the latest information. figure 5. application circuit for one-step conversion (mode 1) gnd +5.6-24v in q1 +v2_5s vsen ugate phase ISL6224 + + c1 c2 330f l1 1/2 fds6912a 56f 1f 6.4h gnd 3 7 10 13 2 1 11 15 pgnd lgate q2 6 8 isen risen tbd 9 c6 0.1f boot vin 12 en cr1 4 (3a) 0.015f 14 pgood c4 r4 soft 2/2 fds6912a + vcc 33f c3 fccm 16 +5.0v cc 5 vout r2 tbd r3 c5 c6 ocset ISL6224
12 figure 6. application circuit for two-step 300khz conversion (mode 2) gnd q1 +v2_5s vsen ugate phase ISL6224 + 330f l1 1/2 fds6912a 6.4h gnd 3 7 10 13 2 1 11 15 pgnd lgate q2 6 8 isen risen tbd 9 c4 0.1f boot vin 12 en cr1 4 (2a) ocset 0.015f 14 pgood c2 r4 soft 2/2 fds6912a + 33f c1 vcc fccm 16 +5.0v cc 5 vout r5 r2 tbd r3 c5 c6 figure 7. application circuit for two-step 600khz conversion (mode 3) r2 tbd gnd q1 +v2_5s vsen ugate phase ISL6224 + 330f l1 1/2 fds6912a 6.4h gnd 3 7 10 13 2 1 11 15 pgnd lgate q2 6 8 isen risen tbd 9 c4 0.1f boot vin 12 en cr1 4 (2a) 0.015f 14 pgood c2 r4 soft 2/2 fds6912a + vcc 33f c1 fccm 16 +5.0v cc 5 vout r3 ocset c5 c6 ISL6224
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6224 shrink small outline plastic packages (ssop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. converted millimeter dimen- sions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m b s e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m16.15a 16 lead shrink narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.061 0.068 1.55 1.73 - a1 0.004 0.0098 0.102 0.249 - a2 0.055 0.061 1.40 1.55 - b 0.008 0.012 0.20 0.31 9 c 0.0075 0.0098 0.191 0.249 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.99 4 e 0.025 bsc 0.635 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 2/02

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